A system-on chip (SOC) is an integrated circuit including, within a single chip, a plurality of circuits for digital signals, analog signals, and high-frequency waves. As shown in FIG. 11, device properties are deteriorated by interactions between circuit blocks, especially by digital switching noises coupled with analog circuits and RF circuits via a silicon substrate. In a field of CMOS-hybrid-device design, it is a well-known measure to use a deep N−well in order to decrease coupling of the digital switching noises via the substrate. However, in case the RF circuits are integrated within a single chip, interference between RF circuit blocks (electric coupling via the substrate and magnetic coupling over the substrate) needs to be considered. When a frequency in use is increased, RF coupling becomes stronger, accordingly. Moreover, an RF passive element having a large area, such as a spiral inductor, is easily coupled with the silicon substrate and an adjacent device. For example, if an input of a low noise amplifier (LNA) is coupled with a VCO that operates at a 1.5 GHz-RF frequency, sensitivity for detecting an antenna signal (usually several micro volts) is decreased due to a high-voltage signal (typically up to one volt) of the VCO.
In order to reduce influences of the coupling between RF devices, such as spiral inductor-spiral inductor coupling, the following technologies are proposed:    (1) Creating a large space between interfering devices;    (2) Providing patterned ground shield layers below spiral inductors (“On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's”, IEEE Journal of Solid-State Circuits, Vol. 33, No. 5, May 1998, pp. 743–752) (hereinafter “non-patent publication 1”);    (3) Deep trench guard technology (“Deep Trench Guard Technology to Suppress Coupling between Inductors in Silicon RF ICs”, 2001 IEEE) (hereinafter “non-patent publication 2”);    (4) Metal wire shield technology in which signal lines are surrounded at least on three sides by faraday cage (U.S. Pat. No. 6,307,252 (date of patent: Oct. 23, 2001)) (hereinafter “patent publication 1”);    (5) Metal cage shield technology in which metal wires are surrounded (Japanese Publication for Unexamined Patent Publication, Tokukaihei 10-256250 (publication date: Sep. 25, 1998)) (hereinafter “patent publication 2”).
An object of the foregoing technologies is to decrease capacitive coupling between a circuit block and a metal connection line by means of metal shield structures. The shield structures are connected with a GND. These conventional structures (EMC EXPO 1996) are similar to a technology (in which circuits are isolated from each other and EMI is decreased) used essentially for a PCB, “Future EMC Trends in PC Board Design”, Jun. 16 to 19, 1986, EMC EXPO 1996, available via Internet <URL: http://www.blackmagic.com/ses/bruceg/EMC/futurePCB.html> (hereinafter “non-patent publication 3”).
However, the foregoing methods have the following problems.
If a large space is created between interfering devices, a chip size and costs are increased.
If patterned GND shields are provided below the spiral inductors, a Q factor of the spiral inductors is decreased. Moreover, this technology is effective in an RF frequency band (coupling reduction via the substrate), but is not effective in reducing electromagnetic coupling (magnetic coupling over the substrate).
The technology of the non-patent publication 2 is not compatible with a normal CMOS process, and is therefore expensive.
The technology of the patent publication 1 prevents noises in metal wires. Therefore, although metal wires are shielded by the technologies of the patent publications 1 and 2, pick-up noises and coupling noises that are transmitted from the silicon substrate or via the silicon substrate cannot be suppressed.
Furthermore, none of the foregoing technologies deal with interactions with active transistors that are such as to amplify the coupling. For example, FIG. 12 illustrates a test pattern including (i) a spiral inductor and (ii) transistors provided adjacent to the spiral inductor. When a signal is supplied to the spiral inductor, ideally a signal measured at drains of the transistors should be zero, without any coupling.
However, as is clear from FIG. 13, a relationship between (i) an input-output connectivity (S21) and (ii) a frequency clearly indicates an occurrence of coupling. From FIG. 13, it is found that the input-output connectivity increases in a high-frequency domain even when the transistors are OFF (Id=0), due to coupling caused by paths in the substrate.
On the other hand, if the transistors are ON, signals are transferred due to electromagnetic coupling between the spiral inductor and gate lines of the transistors.
In hybrid-signal ICs, the deep N−well technology is generally used in order to decrease digital noise coupling that occurs via the silicon substrate. Thus, the deep N−well technology is used in the structure of the spiral inductor and the transistors shown in FIG. 12. The deep N−well technology has an effect of decreasing a value of the S21 by approximately 5 dB, but is still insufficient for a severe applied device such as an RF LNA.